NVIDIA Has a Memory Problem – Why HBM and Memory Stocks May Be the Better AI Investment

Executive thesis

For the last several years, the AI hardware trade has essentially been the NVIDIA trade. Investors who wanted exposure to artificial intelligence bought NVIDIA because NVIDIA controlled the dominant accelerator ecosystem, CUDA created an extraordinary software moat, and hyperscalers were willing to spend billions of dollars buying almost every accelerator the company could deliver.

But the economics of AI infrastructure are beginning to change. The next bottleneck may not be the GPU itself. It may be the memory sitting next to it.

Foxorox thesis:

The next stage of the AI infrastructure cycle may be increasingly defined by HBM scarcity rather than GPU scarcity.

If NVIDIA wins, HBM suppliers win. If AMD gains market share, HBM suppliers still win. If Google, Amazon, Meta or other hyperscalers deploy more custom AI ASICs, HBM suppliers can still win.

For this reason, at current forward valuations, our preferred risk/reward exposure to the AI semiconductor cycle is:

MEMORY > NVIDIA > AMD

This does not mean NVIDIA is suddenly a weak company. NVIDIA still possesses the strongest software ecosystem in accelerated computing, extremely high profitability, powerful networking assets and a uniquely integrated AI factory architecture.

The investment argument is different. NVIDIA must defend a dominant position while absorbing the consequences of rising component costs. The memory manufacturers supply one of the critical components required by almost every serious competing AI architecture.

1. NVIDIA is reportedly raising AI server prices by more than 15%

In August 2026, reports emerged that some of NVIDIA's largest customers had been informed that prices of servers containing NVIDIA AI chips would rise by more than 15% in many configurations. The increases are expected to affect systems shipped in early 2027, including systems based on Grace Blackwell and Vera Rubin.

The important detail is the reason. The reported price increase is being driven primarily by rapidly rising memory-chip costs.

This distinction matters enormously for investors. If NVIDIA raises prices because customers are willing to pay more for superior GPU performance, NVIDIA captures the incremental value. If NVIDIA raises prices because HBM and other memory costs have increased, a meaningful portion of the higher system price simply flows upstream through the supply chain.

A higher NVIDIA system price is therefore not automatically evidence of stronger NVIDIA economics. It may instead be evidence that the bargaining power of memory suppliers is increasing.

Source: Reuters, August 22, 2026. NVIDIA had not officially commented on the reported increases at the time of the report.

2. HBM is becoming the real bottleneck

Modern AI accelerators cannot efficiently operate with conventional memory architectures alone. They require enormous memory bandwidth, which is why multiple DRAM dies are stacked vertically and positioned extremely close to the accelerator.

Every accelerator generation is becoming more memory intensive. TrendForce expects NVIDIA Rubin Ultra to increase HBM capacity per GPU to as much as approximately 384 GB in its originally discussed high-capacity configurations. At the same time, AI ASIC platforms such as Google's TPU are expected to increase HBM demand.

The simplified demand chain is:

More AI compute → more accelerators → more HBM per accelerator → more DRAM wafer capacity consumed → tighter conventional DRAM supply → higher memory prices.

This is what makes the present cycle different from a simple GPU boom. The AI accelerator is consuming not just an expensive chip but an increasingly scarce memory resource.

3. The critical number: 30% of DRAM wafer input

TrendForce estimates that HBM wafer input among the three largest memory suppliers will represent approximately 18% of total DRAM wafer input at the end of 2025, 22% at the end of 2026 and approximately 30% at the end of 2027.

That difference is one of the most important facts in the entire semiconductor investment case. HBM consumes a disproportionate amount of wafer capacity compared with the number of bits delivered.

Therefore the more aggressively AI customers demand HBM, the more conventional DRAM production is indirectly constrained.

TrendForce also expects meaningful production from several new DRAM capacity projects to arrive only gradually. New capacity may begin coming online in 2027, but substantial output contributions are not expected until 2028.

The demand response can happen in quarters. The supply response takes years. That time mismatch is the foundation of memory pricing power.

Sources: TrendForce – June 2, 2026 and TrendForce – July 30, 2026.

4. NVIDIA does not control HBM

NVIDIA designs extraordinary accelerators, CPUs, networking systems and software. But it does not manufacture HBM.

The global high-bandwidth memory market is concentrated primarily around:

NVIDIA therefore has to compete for the same memory supply that AMD, custom ASIC designers and other accelerator platforms require.

This creates a major asymmetry. NVIDIA must win the accelerator competition. The HBM manufacturer can supply whoever wins.

5. AMD does not solve the HBM problem

AMD is the most obvious large-scale challenger to NVIDIA. Its Instinct roadmap and rack-scale systems can capture significant AI infrastructure market share.

But from the memory producer's point of view that does not reduce demand. AMD accelerators also require enormous amounts of HBM.

This is why memory is becoming a particularly interesting position in the AI value chain. The memory supplier does not necessarily need to predict the winning accelerator architecture.

6. HBM scarcity is already influencing accelerator architecture

The memory constraint is becoming serious enough to influence product design. TrendForce reported in August 2026 that NVIDIA had expanded evaluation of Rubin Ultra memory configurations beyond the originally discussed 12-high HBM4E design to include lower-capacity alternatives such as 8-high HBM4E and HBM4 configurations.

Several cloud-service providers were also reported to be evaluating lower HBM capacity for next-generation in-house AI ASICs.

TrendForce expects HBM bit shipments to grow approximately 50–60% year over year in 2027, but still not sufficiently to keep pace with demand growth.

When memory availability begins influencing the architecture of the accelerator itself, memory is no longer a secondary component. It has become a system-level constraint.

Source: TrendForce – August 4, 2026.

7. Why not simply build more HBM factories?

If HBM is so profitable and supply is constrained, the obvious economic response appears simple: build more factories.

But semiconductor manufacturing does not respond like an ordinary manufacturing sector. A competitive DRAM/HBM manufacturing complex requires billions of euros, hundreds of specialized process tools, sophisticated utilities, advanced process IP, highly trained engineers and years of qualification.

The barrier is not only capital. It is technology, yield and know-how.

To illustrate the scale of the problem, Foxorox constructed a conceptual model of a new European 300 mm memory manufacturing campus.

8. Foxorox model – building a European HBM factory

The hypothetical project is not designed to immediately replicate the largest Samsung, SK hynix or Micron campuses. Instead, the first phase assumes:

The campus combines two critical activities:

DRAM wafer fabrication + HBM advanced packaging.

The same strategic platform could also support automotive, industrial and server DRAM, providing a degree of product diversification during different phases of the memory cycle.

9. What would have to be built?

The campus would also require ultra-pure water production, industrial wastewater treatment, gas farms, a dedicated process-gas distribution system, chemical storage and delivery, backup power for critical systems, clean dry air, vacuum, chilled water, highly stable HVAC and sophisticated fire and life-safety infrastructure.

10. The machine park – hundreds of tools before one HBM stack exists

A memory fab requires a repeated sequence of lithography, deposition, etch, implant, cleaning, planarization, inspection and measurement steps. The same wafer may pass through many categories of equipment repeatedly.

The conceptual total is approximately:

~300–500 major semiconductor manufacturing tools before the advanced HBM packaging line is included.

The exact number cannot be established without a specific licensed DRAM process, target node, mask count, process flow, tool throughput and redundancy strategy. The purpose of the model is to show the order of magnitude.

11. Wafer fabrication still does not give you HBM

After DRAM dies are fabricated, the manufacturer still needs to transform them into a high-bandwidth memory package.

A simplified process is:

300 mm DRAM wafer → wafer test → TSV processing → wafer thinning → dicing → die stacking → advanced bonding → package integration → burn-in → final test.

HBM therefore requires a second highly specialized manufacturing ecosystem. This includes wafer thinning, TSV-related processing, extremely accurate die placement, bonding, stacking, thermal management and high-speed test capability.

This is why advanced packaging has become a strategic bottleneck almost as important as wafer fabrication itself.

12. Micron provides a real-world benchmark: $7 billion for HBM packaging

Micron announced a new advanced HBM packaging facility in Singapore with an investment of approximately $7 billion.

This is an important benchmark because the project demonstrates how expensive the back end of the HBM supply chain has become.

$7 billion is not the cost of creating an entire greenfield leading-edge DRAM ecosystem. It is a real-world indication of the enormous capital intensity of advanced HBM packaging capacity itself.

Micron has simultaneously been expanding DRAM manufacturing in the United States, including a broader approximately $200 billion U.S. manufacturing and R&D vision that includes leading-edge fabs, HBM packaging and research.

Sources: Micron – Singapore HBM advanced packaging facility and Micron – U.S. memory manufacturing expansion.

13. Foxorox CAPEX model – European 10k wafer/month DRAM + HBM campus

Our preliminary conceptual Phase I cost model is as follows. These figures are not supplier quotations and should be interpreted as an order-of-magnitude investment model for feasibility analysis.

The resulting first-stage capital requirement is approximately:

€5–8 BILLION
for a serious first-stage European DRAM + HBM manufacturing project.

Expansion toward 20,000 wafer starts per month could eventually take cumulative investment toward approximately:

€8–12+ BILLION

The final investment could be materially higher for a true leading-edge greenfield project depending on process generation, EUV requirements, redundancy, packaging technology, local infrastructure and the cost of acquiring or licensing process technology.

14. Capital alone is not enough

Assume an investor provides €8 billion tomorrow. The factory still cannot simply begin producing competitive HBM.

It requires:

• DRAM process technology,
• intellectual property and process recipes,
• experienced integration engineers,
• equipment engineers,
• yield-management expertise,
• HBM packaging know-how,
• supplier qualification,
• customer qualification,
• and years of accumulated manufacturing knowledge.

Buying ASML, Applied Materials, Lam Research, Tokyo Electron or KLA equipment is not equivalent to buying a functioning DRAM process.

The most difficult asset is not the building. It is the process knowledge that makes the building economically productive.

A realistic new European memory project would therefore probably require a joint venture, technology license, acquisition, strategic partnership or participation by an existing memory producer.

15. Why the enormous barrier to entry supports HBM pricing

This manufacturing model explains why memory shortages cannot be solved quickly.

A hyperscaler can approve another multi-billion-dollar AI deployment within a budgeting cycle. A memory manufacturer cannot create another high-yield advanced DRAM fab in the same time frame.

The response requires:

• site selection,
• permitting,
• cleanroom construction,
• utility construction,
• tool procurement,
• tool installation,
• process qualification,
• yield ramp,
• HBM packaging qualification,
• and customer validation.

This creates the unusual situation in which HBM demand can move very rapidly, while meaningful additional supply moves slowly.

16. The investment question: NVIDIA, AMD or memory?

The manufacturing bottleneck becomes even more interesting when combined with current valuation.

The five companies represent very different business models:

17. Forward valuation comparison – 2026 to 2028

The valuation gap is substantial. The following figures are approximate consensus valuation snapshots reviewed in August 2026. They change continuously with share prices and analyst estimates.

* NVIDIA fiscal-year periods are not perfectly aligned with calendar-year periods used by the Korean companies. Micron also operates on an August fiscal year. The table is intended as a comparative valuation snapshot rather than a perfectly synchronized accounting-period comparison.

The difference is remarkable. An investor is paying only a fraction of the forward earnings multiple for SK hynix or Samsung that the market assigns to NVIDIA, and an even smaller fraction of AMD's multiple.

The central valuation question is therefore not whether NVIDIA is a better company. It is whether NVIDIA is a better stock at the price being paid.

18. EPS growth – memory earnings are exploding

The apparently low memory multiples exist because the market still views memory as one of the most cyclical major semiconductor sectors. That concern is legitimate.

But the present earnings expansion is extraordinary. Rising DRAM pricing, HBM demand and very high AI-related memory utilization have produced a dramatic earnings reset across the memory industry.

For Samsung in particular, consensus estimates imply an extraordinary increase in EPS from depressed prior-cycle levels. This should not be extrapolated indefinitely. The important point is that memory pricing changes profitability extremely quickly.

19. Free cash flow – the memory cycle is turning into cash

Historically, the major criticism of memory companies was simple: profits arrived at the top of the cycle and then disappeared into new factories.

That risk remains. But the scale of current cash generation is becoming difficult to ignore.

Samsung's shareholder-return framework allocates a substantial portion of free cash flow to shareholders, and Reuters reported in August 2026 that the company could return up to approximately 110 trillion won, or roughly $80 billion, to shareholders in 2026 through dividends and buybacks depending on final board decisions.

SK hynix also announced a very large share-repurchase and cancellation program and plans to return more than 50% of cumulative free cash flow generated over 2025–2027 to shareholders.

This matters because it changes the character of the memory cycle. The present boom is not generating only accounting profits. It is producing cash large enough to fund both enormous capacity investments and unprecedented shareholder distributions.

Forward FCF yields for memory companies can screen at extremely high levels during a supercycle. Those numbers should not be treated as normalized sustainable yields because they are highly sensitive to DRAM pricing, HBM pricing, CAPEX timing and working capital.

For NVIDIA and AMD, free-cash-flow dynamics are structurally different because both are fabless. They do not have to fund multi-billion-euro wafer fabs directly. That is an enormous advantage — but it also means the physical manufacturing bottleneck belongs to their suppliers.

20. CAPEX 2026–2028 – the cost of defending the bottleneck

Capital intensity is where memory producers and accelerator designers differ most.

The exact annual numbers for SK hynix and Samsung are difficult to reduce to one clean 2026–2028 figure because the companies are simultaneously executing multiple multi-year megaprojects whose timing depends on market conditions and board approvals.

The direction, however, is unambiguous. Memory manufacturers are committing enormous sums to expand capacity. Micron alone has outlined an approximately $200 billion broader U.S. manufacturing and R&D vision, while its Singapore HBM packaging project is approximately $7 billion. South Korea has announced semiconductor investment programs involving hundreds of trillions of won of future projects by Samsung and SK hynix.

The high CAPEX is simultaneously the memory industry's greatest weakness and one of its strongest moats.

21. Relative valuation – the simplest comparison

This table does not tell us that SK hynix is automatically a better company than NVIDIA. It tells us that the market is asking investors to pay dramatically different prices for exposure to the same AI infrastructure cycle.

22. Why NVIDIA deserves a premium

The memory thesis should not ignore NVIDIA's extraordinary strengths. NVIDIA has built assets that memory manufacturers do not possess:

• CUDA and CUDA-X,
• a massive developer ecosystem,
• NVLink and NVSwitch,
• ConnectX networking,
• Spectrum-X Ethernet,
• InfiniBand,
• BlueField DPUs,
• rack-scale architectures,
• AI Enterprise software,
• and an enormous installed base.

This integrated AI-factory ecosystem justifies a major valuation premium. The argument is not that NVIDIA should trade at the same P/E as a cyclical memory company.

The argument is that when NVIDIA trades at many times the forward multiple of memory producers, while those suppliers gain pricing power over a critical component NVIDIA itself needs, the risk/reward equation becomes less obvious than the market narrative suggests.

23. Why AMD's valuation may be the most difficult

AMD is strategically important because it gives hyperscalers a credible second accelerator platform. Its success could reduce NVIDIA's pricing power and weaken NVIDIA's near-monopoly economics.

But at approximately 37–38x estimated 2027 earnings in the current consensus snapshot, investors are already paying for major future Instinct success.

AMD therefore has to execute on several fronts:

• deliver competitive accelerator performance,
• scale rack-level systems reliably,
• improve ROCm continuously,
• convert announced hyperscaler deployments into revenue,
• build networking capabilities,
• and maintain attractive economics despite the same rising HBM costs affecting NVIDIA.

And here lies the paradox:

If AMD succeeds in taking meaningful market share from NVIDIA, one of the cleanest second-order beneficiaries may still be the company supplying AMD's HBM.

24. The memory supplier does not need to pick the GPU winner

The strongest part of the memory investment thesis can be summarized through scenario analysis.

The memory supplier is therefore positioned one layer deeper in the infrastructure stack. That does not eliminate cyclicality, but it reduces dependence on choosing the winning accelerator vendor.

25. The biggest risk to the memory thesis

Memory is not a risk-free investment. Historically, the industry has repeatedly demonstrated the same pattern:

Prices rise → profits explode → CAPEX explodes → capacity rises → oversupply develops → prices collapse.

The most important bear case is therefore that the present HBM/DRAM shortage triggers too much capacity expansion and ultimately recreates the classical memory down-cycle.

There are additional risks:

• AI capital expenditure could slow,
• HBM content growth could moderate,
• yield improvements could release more effective capacity,
• new fabs could ramp faster than expected,
• Chinese memory producers could increase competitive pressure,
• and customers could redesign accelerators around lower memory content.

TrendForce's August report that accelerator designers are already evaluating lower-HBM configurations shows that high memory prices eventually create demand elasticity.

The memory thesis is strongest while supply remains structurally constrained. It becomes much weaker if the industry overbuilds.

26. Why the present cycle may last longer than a normal DRAM cycle

There are nevertheless several reasons why this cycle could remain tighter for longer.

• HBM consumes disproportionate wafer capacity.
• HBM requires sophisticated advanced packaging in addition to DRAM fabrication.
• AI demand is coming simultaneously from NVIDIA, AMD and custom ASICs.
• New leading-edge fabs require years to build and qualify.
• HBM generations are evolving rapidly, forcing continuous technical investment.
• Server CPU memory demand is also rising.
• Automotive and industrial memory provide additional long-duration demand.

Micron has previously forecast an HBM total addressable market growing at roughly 40% CAGR toward approximately $100 billion by 2028. That would make the HBM market alone larger than the entire DRAM market was only a few years earlier.

If that trajectory proves approximately correct, the industry is not merely reallocating existing memory demand. It is building a new high-value memory category at extraordinary speed.

27. European strategic opportunity

The current shortage also exposes a structural weakness in Europe. Europe has a major automotive industry, industrial electronics, energy infrastructure and a rapidly growing data-center market, but very limited large-scale DRAM/HBM manufacturing.

A rational European strategy would not necessarily begin by trying to replicate the most advanced Asian memory campuses on day one.

A staged project could be:

The economic barrier remains enormous — our conceptual initial manufacturing campus requires approximately €5–8 billion — but that is precisely why existing memory capacity has strategic value.

28. Foxorox AI semiconductor ranking

The ranking is a Foxorox analytical view based on the valuation snapshot, competitive position, AI exposure and supply-chain structure discussed in this article. It is not investment advice.

29. Final investment comparison

The investment case can be reduced to the number of assumptions required for each company.

NVIDIA

An NVIDIA investor assumes that:

• AI infrastructure spending remains enormous,
• NVIDIA maintains dominant accelerator share,
• Rubin and subsequent architectures execute successfully,
• custom ASICs do not take excessive share,
• AMD remains a manageable competitor,
• customers tolerate higher system pricing,
• and rising HBM costs do not materially damage margins.

AMD

An AMD investor assumes that:

• AMD captures significant accelerator share,
• ROCm continues improving rapidly,
• large announced deployments convert to material revenue,
• rack-scale systems execute reliably,
• and future EPS rises sufficiently to justify a very high present forward multiple.

Memory

A memory investor's thesis is simpler:

• AI compute continues expanding,
• HBM content per accelerator remains high,
• wafer and packaging capacity remain constrained,
• and industry supply discipline prevents a rapid oversupply cycle.

The memory thesis does not require NVIDIA to lose. It does not require AMD to win. It requires the AI industry to keep consuming enormous quantities of high-bandwidth memory.

30. Foxorox conclusion – MEMORY > NVIDIA > AMD

NVIDIA remains the dominant AI accelerator company. Its competitive advantage is no longer located only inside the GPU. It exists across GPU, CPU, networking, software, libraries, orchestration, OEM relationships, installed base and deployment experience.

AMD can become a powerful number-two supplier and may capture a meaningful share of hyperscale deployments. That could create substantial growth for AMD.

But both companies require the same scarce resource: high-bandwidth memory.

HBM manufacturers currently benefit from a highly unusual combination:

• rapid AI demand growth,
• limited supply,
• extreme barriers to new capacity,
• growing wafer consumption per delivered bit,
• advanced-packaging constraints,
• multiple competing accelerator customers,
• and forward valuation multiples dramatically below NVIDIA and AMD.

Foxorox final thesis:

At current consensus valuations, we believe the more attractive risk/reward exposure to the next stage of the AI semiconductor cycle may be the memory producers rather than the accelerator designers.

MEMORY > NVIDIA > AMD

If NVIDIA wins, memory wins.
If AMD gains share, memory wins.
If hyperscalers move toward custom ASICs, memory can still win.

NVIDIA must defend the winning architecture.
The memory producer can sell the bottleneck to whoever wins.

For years investors asked:

How many NVIDIA GPUs will the world need?

The more important question for the next stage of the AI cycle may be:

Where will all the memory come from?

And if creating a serious new European DRAM/HBM manufacturing campus requires approximately €5–8 billion in the first stage, hundreds of semiconductor tools, advanced process IP, difficult HBM packaging technology and several years before meaningful high-yield production, the answer is unlikely to arrive quickly.

That scarcity may ultimately allow memory manufacturers to capture a larger share of the economics of the AI infrastructure boom than investors currently expect.

Written by Pawel Demczuk, MSc
Foxorox AI Analyzer